In a manufacturing process of a semiconductor memory, a defect is generated on a chip, caused by dust on a surface of a wafer, uneveness in abrasive in polishing the surface of the wafer, and so on. When a small defect is generated on a chip, the chip itself is regarded as a defective product although only a memory cell having the defect portion is defective and other portions operate normally. It is possible to improve a manufacturing yield by providing a spare memory cell on the chip of the semiconductor memory and replacing read/write data for a defective memory cell with data for the spare memory cell. For this reason, it has become popular with the increase in the capacity of the semiconductor memory to provide a redundancy circuit that contains a spare memory cell and a control circuit.
Relationships between a memory cell and a spare memory cell on a chip are now explained with reference to FIG. 1. As shown in FIG. 1A, a memory block 71 has segments 71-0, 71-1, . . . . A segment is a unit which is designated for repairing a defective memory cell when a defect is generated. A redundancy memory block 72 has redundancy segments 72-0 and 72-1 that substitute for the segments including the defective memory cells. When a size of a defect 75 generated in the memory block 71 is small, the defect 75 fits into only the single segment 71-0 of the memory block 71, as in the case of an example shown in FIG. 1A. Information stored in a memory cell group associated with the defect 75 is repaired by the redundancy segment 72-0 in the redundancy memory block 72.
However, as a process scale is miniaturized year by year and the size of the memory cell is reduced, the size of the defect becomes relatively larger in comparison with the size of the memory cell, as shown in FIG. 1B. As a result, the defect does not fit into a single segment but is generated over adjacent successive segments. For this reason, even when the defect 75 having the same size as the defect shown in FIG. 1A is generated, three segments from the segments 73-0 to 73-2 are defective in the example shown in FIG. 1B. Therefore, a redundancy memory block 74 that repairs the defect needs three or more redundancy segments. As described above, a single redundancy segment can repair the defect 75 in the example shown in FIG. 1A. However, in the present day when the process is miniaturized, three redundancy segments are necessary, and defective memory cells concentrates on a specific memory block and is unevenly distributed, as shown in FIG. 1B.
On the other hand, a defective address indicating a memory cell group associated with the defect 75 is held by a redundancy circuit. A fuse is often used for holding the defective address. In the case of FIG. 1A, the fuse holds an address indicative of the segment 71-0 as the defective address. When the memory block 71 is accessed, and when the defective address held by the fuse matches an access address, the segment 72-0 in the redundancy memory block 72 is accessed.
In recent years, address information of a memory is increased due to the increase in the memory capacity. As mentioned above, a capacity of the redundancy memory itself also has to increase. The increase in the capacity of the redundancy memory leads to an increase in the number of fuses which hold the defective addresses.
A configuration of a conventional redundancy memory is described with reference to FIG. 2. As shown in FIG. 2, a system has sub mats 81-0 to 81-7, a sub mat decoder 82 and a column decoder 83, where a redundancy circuit is provided for every sub mats. In general, redundancy circuits are provided in both a row side and a column side. For simplification of the explanation, only the row side is represented in FIG. 2, and the redundancy circuit in the row side will be explained. Here, an address X0 to X13 of 14 bits is inputted as a row address. The address X11 to X13 is used for selecting one of the eight sub mats. The address X3 to X10 is used for selecting one of 256 main word lines MWD of the selected sub mat. The address X0 to X2 is used for selecting one of eight sub word lines SWD. Since eight sub word lines SWD are related to one main word line MWD with regard to word lines, each of the sub mats has 2048 word lines in total (the 256 main word lines×the eight sub word lines). Thus, FIG. 2 shows a memory that has eight spare word lines for the 2048 word lines in each of the sub mats.
The sub mats 81-0 to 81-7 are selected by sub mat selection signals SM0 to SM7 generated by the sub mat decoder 82, respectively. The sub mat 81-0 is provided with a memory cell array 85-0 which is a memory block, a row address decoder 86-0, a redundancy memory cell array 87-0 which is a redundancy memory block, a redundancy row address decoder 88-0, redundancy ROM circuits 91-0-0 to 91-0-7, a sub word decoder 89-0, an AND circuit 93-0, and an OR circuit 94-0. It should be noted that additional numbers attached to reference numerals are given to make a distinction between similar components, and are omitted when the distinction is not necessary. Also, the other sub mats 81-1 to 81-7 have the same configuration as the sub mat 81-0. The only difference is that respective of SM1 to SM7 are inputted as the sub mat selection signals SM. Therefore, description will be given only on the sub mat 81-0, and explanation of the other sub mats 81-1 to 81-7 will be omitted.
In the sub mat 81-0, the memory cell array 85-0 is a group of memory cells of a main body. A memory cell row connected to a word line selected by the row address decoder 86-0 and the sub word decoder 89-0 is activated, and data of the memory cell is amplified by a sense amplifier 84-0. Further, a sense amplifier is selected by a column address decoder 83, and the data is transmitted to an I/O circuit (not shown).
The row address X3 to X10 is inputted to the row address decoder 86-0. The inputted row address is decoded, and one of the 256 main word lines MWD is selected and activated. The sub word decoder 89-0 receives the row address X0 to X2, selects one of the eight sub word lines SWD, and activates the sub word line SWD connected to the activated main word line MWD. Thus, one of the 2048 word lines is activated by the row address decoder 86-0 and the sub word decoder 89-0.
The redundancy memory cell array 87-0 is a redundancy memory for repairing a defective portion of the memory cell array 85-0. A redundancy main word line RMWD in the redundancy memory cell array 87-0 is activated by the redundancy row address decoder 88-0.
The redundancy row address decoder 88-0 decodes a row address in the redundancy memory cell array 87-0. Redundancy selection signals RE outputted from the redundancy ROM circuits 91-0-0 to 91-0-7 is inputted to the redundancy row address decoder 88-0, and a redundancy main word line RMWD is activated. Thus, the redundancy row address decoder 88-0 activates the redundancy main word line RMWD, when any of the redundancy selection signals RE-0-0 to RE-0-7 is activated.
The redundancy ROM circuits 91-0-0 to 91-0-7 hold defective addresses which indicate positions of the defects in the memory cell array 85-0 to be replaced, and determines whether the redundancy memory cell array 87-0 is selected or not. When the redundancy memory cell array 87-0 is selected, the redundancy selection signal RE is activated. With respect to the defective addresses in the memory cell array 85-0, address information corresponding to the row address X0 to X10 are programmed in fuses provided to the redundancy ROM circuits 91-0-0 to 91-0-7. When the memory cell array 85-0 is accessed, the redundancy ROM circuits 91-0-0 to 91-0-7 compare the address information programmed in the fuses with the row address X0 to X10 to be accessed. In a case of match as a result of the address comparison, the redundancy ROM circuits 91-0-0 to 91-0-7 determines that the row address to be accessed is the defective address, and activates the redundancy selection signal RE. In a case of mismatch as a result of the address comparison, the memory cell array of the main body is to be selected, and the redundancy selection signal RE is not activated.
The sub word decoder 89-0 decodes the lower bits X0 to X2 of the row address, activates a sub word line SWD connected to the main word line MWD activated by the row address decoder 86-0, and activates the word line of the memory cell row to be accessed. When a defective address is accessed, the redundancy memory cell array 87-0 instead of the memory cell row specified by the row address should be accessed. It is therefore necessary to invalidate the row address inputted to the sub word decoder 89-0, and to access the redundancy memory cell array 87-0 in accordance with the redundancy selection signal RE outputted from a redundancy ROM circuit holding the defective address among the redundancy ROM circuits 91-0-0 to 91-0-7. For this reason, the sub word decoder 89-0 receives the redundancy selection signals RE-0-0 to RE-0-7 outputted from respective of the redundancy ROM circuits 91-0-0 to 91-0-7. When any of the redundancy selection signals RE-0-0 to RE-0-7 is activated, the sub word decoder 89-0 switches a selector of the sub word decoder 89-0 by using an output of the OR circuit. Also, the sub word decoder 89-0 outputs the redundancy selection signal RE as a signal for selecting the redundancy sub word line RSWD instead of a signal obtained by decoding the lower three bits of the row address.
The AND circuit 93-0 generates a redundancy activation signal BE for activating the redundancy ROM circuits 91-0-0 to 91-0-7. A logical multiplication of the sub mat selection signal SM0 indicating that the sub mat 81-0 is selected and an access activation signal AE indicating that the memory cell is to be accessed is a condition for activating the redundancy ROM circuits 91-0-0 to 91-0-7.
The OR circuit 94-0 receives the redundancy selection signals RE-0-0 to RE-0-7 outputted from the redundancy ROM circuits 91-0-0 to 91-0-7, and outputs a logical addition thereof as a row address decoder killer signal XDK. The row address decoder 86-0 gets into an inactive state, in response to the row address decoder killer signal XDK. Consequently, the memory cell array 85-0 is not activated.
Normal memory access in the above configuration is performed as follows. Here, an operation to read out data stored in the memory cell is explained.
When an access address and an instruction to read data are given, the row address X0 to X13 is validated and the access activation signal AE is activated. The upper row address X1 to X13 is inputted to the sub mat decoder 82, and one of the sub mat selection signals SM0 to SM7 which selects any of the sub mats 81-0 to 81-7 to be accessed is activated. When the row address X11 to X13 is all zero, the row address indicates that the sub mat 81-0 is to be accessed, and the sub mat selection signal SM0 is activated. When the sub mat selection signal SM0 is activated, the AND circuit 93-0 takes the logical multiplication of the access activation signal AE and the sub mat selection signal SM0 to activate the redundancy activation signal BE. The redundancy activation signal BE activates the redundancy ROM circuits 91-0-0 to 91-0-7.
The redundancy ROM circuits 91-0-0 to 91-0-7 store states of the fuses in latch circuits beforehand, at the time of initial setting such as the time of the power activation. Information of the defective addresses held in the latch circuits and the inputted row address X0 to X10 are compared in an address comparator.
In a case of mismatch as a result of the comparison, it is indicated that the memory cell at the address to be accessed has no defect. Therefore, the memory cell array 85-0 is accessed, and the redundancy selection signal RE is not activated. Unless any of the redundancy ROM circuits 91-0-0 to 91-0-7 is activated, the row address decoder killer signal XDK is not activated, and one main word line MWD selected by the row address decoder 86-0 is activated. Similarly, in the sub word decoder 89-0, the output of the OR circuit is not activated, and one sub word line selected based on the row address X0 to X2 is activated. A memory cell row 80 is activated which is connected to a word line selected in accordance with decoding results in the row address decoder 86-0 receiving the row address X3 to X10 and the sub word decoder 89-0 receiving the row address X0 to X2. Data corresponding to the access address is outputted from the memory cell row 80 through the sense amplifier 84-0 selected by the column address decoder 83 to which a column address is supplied.
In a case of match as a result of the comparison, it is indicated that the memory cell at the access address has a defect, and the redundancy memory cell array 87-0 is then accessed. To access the redundancy memory cell array 87-0, a redundancy ROM circuit 91 holding the defective address that matches the access address among the redundancy ROM circuits 91-0-0 to 91-0-7 activates the redundancy selection signal RE. When the redundancy selection signal RE is activated, the OR circuit 94-0 activates the row address decoder killer signal XDK to inactivate the row address decoder 86-0. Consequently, the memory cell array 85-0 is not accessed. The redundancy selection signals RE-0-0 to RE-0-7 are supplied to the redundancy row address decoder 88-0, and a redundancy main word line RMWD in the redundancy memory cell array 87-0 is activated. Since one of the redundancy selection signals RE-0-0 to RE-0-7 inputted to the sub word decoder 89-0 is activated, the selector is switched. Outputted from the sub word decoder 89 is not a signal which selects a sub word line SWD in the memory cell array 85-0 corresponding to the decoding result of the row address X0 to X2 but a signal which selects a redundancy sub word line RSWD specified by the redundancy ROM circuit 91-0.
A memory cell row 92 is activated that is connected to the word line in the redundancy memory cell array 87-0 selected by the redundancy sub word line RSWD specified by the redundancy ROM circuit 91-0. Data corresponding to the access address is replaced by the data of the redundancy memory cell array 87-0 and is outputted from the memory cell row 92 through the sense amplifier 84-0 selected by the column address decoder 83 to which a column address is provided.
In the case of the above example, the number of the fuses holding the defective addresses is eleven per one redundancy ROM circuit 91, which corresponds to the row address X0 to X10 of 11 bits. Also, eight row addresses can be replaced in one sub mat. Therefore, if the defects are detected in 9 or more row addresses in the one sub mat 81, the memory chip cannot be repaired even if there is no defect in the other sub mats 81.
Thus, it is necessary to efficiently conduct a repair by using a redundancy circuit while reducing the chip size by designing circuits dedicated to the redundancy circuit as less as possible. In a case where defects are evenly distributed over a memory block and between memory blocks, it is possible to repair the defective cells by providing redundancy circuits, the number of which is determined stochastically. However, the repair of the defects generated in the memory block is limited by the number of redundancy circuits provided in the block. There is a problem in that the memory chip cannot be repaired when the defective cells concentrate in a particular memory block and the number of addresses to be replaced exceeds the number of redundancy circuits.
Next, a flexible method is explained, which redeems the above-mentioned shortcomings and improves repair efficiency. According to the considered flexible method, a redundancy circuit is not provided for each memory block, but a larger redundancy circuit is provided for a larger memory block. Although the fraction of redundancy circuit size per a memory block is the same, it is possible to repair the defects which are unevenly distributed, since an absolute number of the redundancy circuits handling the memory block is increased.
For example, the redundancy ROM circuit 91 shown in FIG. 2 is replaced by a redundancy ROM circuit 96 shown in FIG. 3. The number of fuses holding the defective addresses is increased by three per a redundancy circuit in comparison with the circuit in FIG. 2, and the access address is compared with the row address X0 to X13. The access activation signal AE is directly supplied to the redundancy ROM circuit 91 such that it is activated whenever any of the sub mats 81-0 to 81-7 is accessed. Then, the redundancy ROM circuit 96 can be used in common in all sub mats 81. In FIG. 2, eight redundancy circuits are provided for each of the sub mats 81-0 to 81-7. According to the redundancy ROM circuit shown in FIG. 3, 64 redundancy circuits shared by respective of the sub mats 81-0 to 81-7 are provided. Thus, even if there are ten defective addresses to be replaced in the sub mat 81-0, the chip can be repaired if there are no defects at all in the sub mats 81-1 to 81-7.
As stated above, the number of fuses holding the defective addresses in the redundancy ROM circuit 96 is fourteen, which corresponds to the row address X0 to X13. Also, the number of defects that can be replaced with in one memory block is 64.
According to the flexible method, although the capability to repair the unevenly-distributed defects is improved, there is a problem that the number of fuses in the redundancy circuit is increased due to the increase in the size of the memory block that is to be replaced.
The size of the fuse is approximately 3 times 60 micrometers, which is very large as compared with the memory cell size being approximately 0.13 square micrometers. Therefore, the number of fuses should be as small as possible. For example, in a case when the memory is divided into 2n memory blocks and m redundancy memory cell rows are provided to each of the memory blocks, the number of the redundancy memory cell rows is m×2′. When the bit number of the address which specifies the redundancy memory cell row is X, the number of fuses provided to the redundancy circuit is (X−n)×m×2n in the former method, and is X×m×2n in the latter method. For example, as compared with a case where the memory is divided into eight (n=3) and eight redundancy circuits are provided in the former case, extra 192 fuses are necessary in the latter case.
As described above, it is important to reduce the number of fuses, as the memory capacity increases and the memory cell is miniaturized. A method which is the combination of the former and the latter methods is also known (e.g. Japanese Laid Open Patent Application JP-P2001-143494A). According to the method, some of the redundancy circuits are allocated to a divided memory block, and the remaining redundancy circuits are allocated to a plurality of division memory blocks.
Also, Japanese Laid Open Patent Application JP-A-Heisei 5-242693 discloses a technique, in which two column lines in a column direction are simultaneously replaced by a redundancy circuit, the redundancy circuit is composed of two redundancy blocks, two redundancy blocks are selected by lower column addresses, and a ROM circuit (a fuse and a program circuit) of the redundancy circuit is used in common to reduce the fuse area and selection circuit.